1. Field of the Invention
The present invention relates to MOS transistors and particularly to MOS transistors, which are suitable for RF power applications and constructed on SOI (silicon on isolator) basis.
2. Description of the Related Art
MOS transistors that are suitable for RF power applications need to have low parasitic capacities to have as little low pass characteristics as possible. A reduction of the parasitic capacities is possible by constructing MOS transistors on an SOI substrate. Such SOI MOS transistors are described, for example, in EP 0562271 A1, WO99/40614 A2 and WO97/24758 A1. The problem of the RF power transistors shown there is that, on the one hand, the overall transistor is divided into individual transistors, called fingers, which are generally disposed in parallel to each other, for obtaining a high transistor width to be suitable as RF power transistor, and that, on the other hand, all terminals of the transistor fingers, i.e. drain, gate and source terminal, are formed on the same semiconductor layer of the SOI substrate. Under these conditions it is difficult to appropriately combine and connect, respectively, the three different terminals of the transistor fingers disposed in parallel to each other at the only two available ends of the parallel transistor fingers. Combining the transistor fingers leads to more expensive and larger housing structures and wirings on the semiconductor layer and also to undesired inductivities at the source terminals by bonding wires.
Among the MOS transistors formed in a single substrate where the drain, source and channel regions are formed in an epitaxial semiconductor layer of a semiconductor substrate and which is less suitable for RF power applications due to the higher parasitic capacities, there are so-called LDMOS transistors, where so-called sinkers, i.e. indiffused deep-reaching regions, make a connection between the source region in the epitaxial layer where the transistor is formed and the chip backside, in that they extend down into the highly doped semiconductor substrate on which the epitaxial layer is. The source terminal is formed as metallization on the back of the chip and the back of the semiconductor substrate, respectively. In these transistors, transistor fingers disposed in parallel to each other can be wired such that the gate and drain terminals are combined on opposite ends of the transistor fingers, while the source terminal is, for example, connected to ground via the back of the chip. For improving, for example, the transistor finger repetition distance and the resistance, U.S. Pat. No. 6,297,533 B1, U.S. Pat. No. 6,063,678 and WO 98/57379 A1 suggest to replace the sinker structures by vias of different types, which connect the source region in the epitaxial layer to the semiconductor substrate lying below.
With regard to FIG. 3, an example of a known HF LDMOS power transistor, which is formed in an epitaxial layer of a semiconductor substrate, is explained in more detail. The power transistor comprises a substrate 100 with an active region 102, wherein the source, gate and channel and drain regions, respectively, of the transistor are formed, as it is indicated in the lower portion of FIG. 3. As can be seen in FIG. 3, in the shown LDMOS transistor for RF power applications, the whole transistor width is divided into individual transistor structures and transistors (fingers), respectively, which are disposed in parallel to each other according to the common configuration.
The active region 102 comprises a plurality of transistor structures T1 to T4. The first transistor structure T1 and the second structure T2 comprise a source region S1, and S2/3 each as well as a gate region G1 and G2 each. Further, the transistor structures T1 and T2 comprise a common drain region D1/2, which is disposed between the two gate structures G1 and G2, as can be seen. In the same way, the transistor structures T3 and T4 comprise a source region S2/3 and S4 each as well as a gate region G3 and G4 each. Similar to the structures T1 and T2, the transistor structures T3 and T4 comprise a common drain region D3/4, which is disposed between the gate regions G3 and G4. As can be seen, the individual transistor structures T1 to T4 are disposed in parallel to one another and extend from a first side 104 of the active region 102 to a second side 106 of the active region 102, which is opposed to the first side 104.
On the substrate 100, adjacent to the first side 104 of the active region 102, a gate terminal 110 is formed, which, in the embodiment shown in FIG. 1a, comprises four finger-shaped portions 110a to 110d, which extend starting from the second side 104 of the active region 102 across the gate regions G1, G2, G3 and G4 in the direction of the second side 106 of the active region 102. Further, adjacent to the second side 106 of the active region 102, a drain terminal 112 is formed, which comprises two finger-shaped portions 112a and 112b, which extend starting from the second side 106 of the active region 102 across the drain regions D1/2 and D3/4. The finger-shaped portions 110c to 110d of the gate terminal 110 as well as of the finger-shaped portions 112a and 112b of the drain terminal 112 are disposed in parallel to each other.
Further, the transistor structure shown in FIG. 3 comprises gate connections 114a and 114b disposed on the second side 106 of the active region 102, to electrically connect the gate regions of adjacent transistor structures. The gate connection 114a is provided to electrically connect the fingers 110a and 110b of the gate terminal 110. In the same way, the gate connection 114b is provided to electrically connect the fingers 110b and 110d of the gate terminal 110. This electrical connection of the fingers 110a/110b and 110c and 110d at the finger end is advantageous to obtain a distribution of an input signal applied to a gate terminal 110, which is as even as possible.
The simple combination of gate terminals and drain terminals of the transistor fingers is enabled by contacting the source terminal across the semiconductor substrate, which is below the epitaxial layer, wherein the structures shown in FIG. 3 are formed. A disadvantage of the RF power transistor of FIG. 3, however, is its inherent higher parasitic capacity due to the well structure in an epitaxial layer of a semiconductor substrate.
U.S. Pat. No. 5,548,150 A describes, with reference to FIGS. 12, 39 and 41, an MOSFET on SOI basis, where a trench structure is formed below the source electrode and filled with a conductive material with high thermal conductivity, whereby the source electrode is brought into thermal contact with the silicon substrate, part of the silicon substrate further serves as a source electrode and the heat dissipation characteristics are improved. While this MOSFET structure enables, on the one hand, the above-described easy contactability of the transistor, and, on the other hand, provides at the same time the advantages of using a SOI substrate with regard to the lower parasitic capacities, it is disadvantageous that the structure cannot be used in any application, for example when the semiconductor substrate of the SOI substrate has to have a high resistance due to a coil to be integrated, so that the same cannot serve as source electrode.